1. Field of the Invention
The present invention relates to field programmable gate array (FPGA) architectures. More particularly, the present invention relates to FPGA architectures with flexible input/output capabilities.
2. The Prior Art
In recent years, field-programmable gate array integrated circuits have established themselves as staples in the electronics industry. Integrated circuit architectures for such products typically comprise an array of logic function modules which may be user configured to implement a large variety of logic functions. A programmable interconnect architecture, comprising a plurality of initially uncommitted interconnect conductors is superimposed over the array of logic function modules to enable custom connections to be made among the inputs and outputs of individual ones of logic function modules. A plurality of input/output (I/O) modules are disposed on the integrated circuit, usually around the periphery of the array, and are used to transfer logic signals to and from the array to off-chip circuit nodes. The I/O modules are connectable to the inputs and the outputs of the logic function modules via the programmable interconnect architecture.
The aforementioned elements of a typical FPGA array may be selectively connected to one another by the use of user-programmable interconnect elements. User-programmable interconnect elements may take several forms such as one-time-programmable antifuse elements, transistors, RAM cells, etc. These forms of user-programmable interconnect elements are known to those of ordinary skill in the art.
An example of a transistor-interconnect-element based FPGA architecture is disclosed in U.S. Pat. No. 4,870,302 to Freeman. Products embodying this type of architecture are marketed by Xilinx, Inc. of San Jose, Calif. In this architecture, transistors controlled by RAM cells are selectively turned on to make interconnections between logic function modules. Another such example is found in U.S. Pat. No. 5,187,393 to El Gamal et al., which uses EPROM or EEPROM transistors. The flexibility of such an architecture due to its reprogrammability is, however, offset to some extent by the relatively high on resistance of the transistors used to implement the interconnections.
Examples of several aspects of antifuse-based FPGA architectures are disclosed in U.S. Pat. No. 4,758,745 to El Gamal et al., U.S. Pat. No. 4,873,459 to El Gamal et al., U.S. Pat. No. 5,073,729 to Greene et al., U.S. Pat. No. 5,083,083 to El Ayat et al., and U.S. Pat. No. 5,132,571 to McCollum et al.
The I/O architectures of prior art FPGA devices usually takes one of two forms. In a first form, exemplified by U.S. Pat. No. 4,758,745, a plurality of I/O modules are disposed on the integrated circuit, preferably located near the periphery of the integrated circuit. Each of the I/O modules may be configured by an end user to be either an input module or an output module by appropriate programming. Examples of typical I/O modules are found in U.S. Pat. No. 5,017,813 to Galbraith et al., and U.S. Pat. No. 5,083,083 to El Ayat et al. (See FIG. 6).
The I/O module is typically directly coupled to an I/O pad and contains both input and output buffers, as well as control circuitry for determining whether the module will function as an input module or an output module. An input node, an output node, and at least one control node of the I/O module are connected to individual conductors in the general interconnect architecture of the integrated circuit whereby the I/O module may be connected to inputs and outputs of logic function modules disposed on the integrated circuit. In such prior-art architectures embodied in FPGA products designed by Actel Corporation, assignee of the present invention, the interconnect conductors associated with the input node, an output node, and at least one control node of the I/O module typically run the length of two to four rows in the array.
The second form of prior-art FPGA I/O architecture simply employs an output conductor and a buffered input conductor connected to an I/O pad on the integrated circuit. The output conductor and the input conductor are extended into the array of logic function modules for a fixed distance, usually enough to provide interconnection to a single logic function module located near the periphery of the integrated circuit. An example of such an architecture is illustrated at page 212 of the QuickLogic 1994 Databook from QuickLogic of Santa Clara, Calif.
While the prior art has been able to provide an arrangement by which inputs may be provided to, and outputs may be obtained from logic function modules in an integrated circuit, there is room for improvement of I/O architectures used in FPGA and other devices.
It is an object of the present invention to provide an I/O architecture for FPGA and other user-programmable integrated circuit devices which is more flexible than the prior-art architectures.
It is an object of the present invention to provide an I/O architecture for FPGA and other user-programmable integrated circuit devices which avoids having to provide fixed location I/O modules.
It is yet another object of the present invention to provide an I/O architecture for FPGA and other user-programmable integrated circuit devices which provides dedicated horizontal and vertical routing conductors for input, output and control signals with numerous segmentation and interconnect element options and variations.
Another object of the present invention is to provide an I/O architecture for FPGA and other user-programmable integrated circuit devices with depopulation of programmable interconnect elements to reduce capacitance and increase speed.
Yet another object of the present invention is to provide an I/O architecture for FPGA and other user-programmable integrated circuit devices with long dedicated horizontal and vertical routing conductors for input and output signals, but with short routing conductors for control signals.
It is a further object of the present invention to provide an I/O architecture for FPGA and other user-programmable integrated circuit devices including series user-programmable interconnect elements on selected routing conductors to allow unused routing conductors to be used for general interconnect.
A further object of the present invention is to provide an I/O architecture for FPGA and other user-programmable integrated circuit devices which allows ganging more than one output buffer to provide increased output drive.